Aerotenna, a Silver member of the Dronecode, has announced a new hardware platform supporting ArduPilot based on the Xilinx® Zynq®-7000 System-on-Chip (SoC). The new platform, named OcPoC (Octagonal Pilot on Chip), is the first platform to run ArduPilot that combines FPGA and ARM architectures. With the new OcPoC platform, Aerotenna plans to meet the needs of the drone community with greatly enhanced processing capability, I/O expansion and much more flexibility in sensor fusion.
OcPoC is engineered to be a ready-to-fly “box” with integrated IMU, Barometer and GPS receiver, and features a CSI-camera interface to support high-resolution video streaming. OcPoC also provides reconfigurable I/Os and sensor integration options to enable developers to power their ideas. The combination of dual ARM cores plus FPGA logic enables a hardware/software co-design approach that places some of the timing-critical processing tasks in the programmable logic. Thus the I/O peripherals and memory interfaces provide near-real-time access speeds, and are more versatile than the ones provided by MCU-based platforms.
Aerotenna has successfully ported the whole ArduPilot system onto OcPoC, running Petalinux. The Zynq configuration bitstream file and Linux boot loader will be provided as a pre-built option to make it easy to set up.
- Xilinx Zynq SoC-based processing structure
- Dual-core ARM processor and FPGA for real-time processing
- Integrated IMU sensors and GPS receiver
- Compatible with ArduPilot flight control system
- Versatile and flexible input/output options
- Efficient octagonal design with flexible sensor integration capabilities
OcPoC Launch Program and Special Dronecode Offer
Aerotenna has also announced the OcPoC Launch program, which gives its applicants the opportunity to beta test OcPoC on different airframes and with other sensors to help perfect OcPoC. The priority of shipment will be given to companies and senior developers who are a part of the Dronecode organization, and may also be exempted from paying the required deposit.